1. Field of the Invention
The present invention relates to a synchronous semiconductor device and, more specifically, to a synchronous semiconductor memory device capable of high speed operation.
2. Description of Background of Art
In a conventional memory, processing of an input address proceeds in most cases simultaneously with processing of data. Here, as to the time of processing until the data is written to a memory cell, the time necessary for processing an address is longer than the time necessary for data processing. Processing of address takes time as it involves complicated processes such as determination of the necessity of redundancy processing for repairing defective memory cell and internal re-addressing. This time limits operation performance of the chip.
FIG. 55 represents the conventional flow of address processing.
Referring to FIG. 55, at the time of writing, an externally input address and data are taken through an input buffer to the semiconductor memory device approximately at the same time. Thereafter, data is distributed to the memory array along a data path. The address, on the other hand, may be subjected to logic conversion or logical processing such as redundancy determination for repairing defect, if any, or a process for generating burst addresses. The time necessary for address processing increases as the process content becomes complicated. After the end of logical processing, decoding takes place for activating a selecting signal YS for column selection. By this time, the data has already been transmitted to the memory array. In other words, the data is kept waiting until the selecting signal YS is activated, and this wasteful wait time limits operation frequency of the chip.
Various and many forms of memories have been proposed to realize high speed operation in recent semiconductor memory devices. High speed operation is also demanded for address processing.
An object of the present invention is to prevent the time necessary for complicated address processing, especially the redundancy determination for repairing defect or the process of internal address conversion from limiting data transmission, and to improve operation performance of a semiconductor memory device.
Another object of the present invention is to increase speed of redundancy determination for a plurality of addresses while suppressing increase in chip area.
A further object of the present invention is to reduce power consumption at the time of self refresh.
Briefly stated, the present invention provides a synchronous semiconductor memory device receiving address signals and control signals in synchronization with an external clock signal and inputs/outputs stored data, including a plurality of memory cell blocks, an address bus and a plurality of selecting circuits.
The plurality of memory cell blocks each includes a plurality of memory cells arranged in a matrix of rows and columns. The address bus is provided common to the plurality of memory cell blocks, and transmits the address signals to each of the plurality of memory cell blocks. The address bus includes an address signal line for time-divisionally transmitting a row address signal designating a memory cell position in the row direction and a column address signal designating a memory cell position in the column direction. The plurality of selecting circuits are provided corresponding to the memory cell blocks, and select a memory cell in response to the address signals from the address bus. Each selecting circuit includes a column selecting circuit holding a data corresponding to the column address signal and selecting a column of the memory cells in response to the column address signal.
According to another aspect, the present invention provides a synchronous semiconductor memory device receiving address signals and control signals in synchronization with an external clock signal and inputting/outputting stored data, including a plurality of memory cell blocks, an address bus, a plurality of redundancy determining circuits, and an address converting circuit.
The plurality of memory cell blocks each include a plurality of memory cells arranged in a matrix of rows and columns. The address bus is provided common to the plurality of memory cell blocks, and transmits the address signals to each of the plurality of memory cell blocks. The address bus includes an address signal line for time divisionally transmitting a row address signal designating a memory cell position in the row direction and a column address signal designating a memory cell position in the column direction. Each memory cell block includes a plurality of normal memory portions holding stored data and a plurality of redundant memory portions for repairing defective memory cell. The address converting circuit generates a plurality of addresses corresponding to the address signals. The plurality of redundancy determining circuits each determine whether the normal memory portions should be substituted for by the plurality of redundant memory portions in response to the address signals. Each redundancy determining circuit includes an address setting unit for setting a substitute address corresponding to an address of a defective memory cell, and plurality of comparing circuits provided corresponding to the plurality of addresses respectively, comparing and detecting matching between the substitute address and the plurality of addresses.
According to a still further aspect, the present invention provides a synchronous semiconductor memory device receiving address signals and control signals in synchronization with an external clock signal and inputting/outputting stored data, including a plurality of memory cell blocks, an address bus, a plurality of selecting circuits, a self refresh control circuit and a refresh address bus.
The plurality of memory cell blocks each include a plurality of memory cells arranged in a matrix of rows and columns. The address bus is provided common to the plurality of memory cell blocks and transmits the address signals to each of the plurality of memory cell blocks. The address bus includes an address signal line for time-divisionally transmitting a row address signal designating a memory cell position in the row direction and a column address signal designating a memory cell position in the column direction. The plurality of selecting circuits are provided corresponding to the memory cell blocks and select a memory cell in response to the address signals from the address bus. Each selecting circuit includes a holding circuit for holding data corresponding to the address signals. The self refresh control circuit generates a refresh address data in a self refresh mode. The refresh address bus transmits the refresh address data to the holding circuit.
Accordingly, an advantage of the present invention is that address related pre-processing is terminated before data arrival in column selection, and therefore input/output of data arriving at the memory block earlier than at a terminal is not limited by the address related pre-processing or the like, whereby high speed data input/output is possible.
Another advantage of the present invention is that, as redundancy determination for a plurality of addresses is performed in parallel, the speed of operation is increased, and that, as the portion for setting the substitute address is shared, chip area is not increased.
A still further advantage of the present invention is that power supply to the decode circuit and the like provided corresponding to the memory cell blocks can be kept off, and therefore power consumption at the time of self refresh can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.